1) Not in this case, no.
2) They can't read on the same clock cycle, one of them will get stalled (which one depends on bus priority configuration, see 2.1.1.1 in the RP2040 datasheet). Unless you are absolutely pushing the last ounce of performance, this doesn't matter.
3) On RP2040, definitely no - all bus transactions are 32-bit and the CortexM0 doesn't split any loads into more than one transaction. I think there's a theoretical exception on RP2350, if you've managed to get a bigger-than-8-bit value that's off alignment, as the CortexM33 can do unaligned loads (which necessarily take two bus cycles to fetch the two halves), and I think those get arbitrated separately so could be non-atomic. But that's a weird special case that shouldn't arise in normal use. All bets are off for datatypes bigger than 32-bit of course.
It's very common to rely on this to do things like single-reader, single-writer circular queues between the cores without locking.
2) They can't read on the same clock cycle, one of them will get stalled (which one depends on bus priority configuration, see 2.1.1.1 in the RP2040 datasheet). Unless you are absolutely pushing the last ounce of performance, this doesn't matter.
3) On RP2040, definitely no - all bus transactions are 32-bit and the CortexM0 doesn't split any loads into more than one transaction. I think there's a theoretical exception on RP2350, if you've managed to get a bigger-than-8-bit value that's off alignment, as the CortexM33 can do unaligned loads (which necessarily take two bus cycles to fetch the two halves), and I think those get arbitrated separately so could be non-atomic. But that's a weird special case that shouldn't arise in normal use. All bets are off for datatypes bigger than 32-bit of course.
It's very common to rely on this to do things like single-reader, single-writer circular queues between the cores without locking.
Statistics: Posted by arg001 — Mon Nov 04, 2024 5:40 pm
