@will-v-pi: sorry, I missed your previous post.
I think I've got it.
So we have to combine the following:
XIP_MAINTENANCE_BASE (0x1800:0000)
XIP_SRAM_BASE (0x1200:0000) - in this case
---- base 0x1A00:0000 = 0x1800:0000 + 0x0200:0000 (offset within 64 MB XIP address space)
bit 13 - cache way (only one way, otherwise will be re-pinned)
bits 12:3 - cache line
bits 2:0 = 0x7: Pin cache set/way at address
I can see the XIP RAM mapped at 0x1200:0000, fully populated with cache data memory.
That was my intention. Thanks !![Smile :)]()
Is there any chance to see the tag memory ?
I think I've got it.
So we have to combine the following:
XIP_MAINTENANCE_BASE (0x1800:0000)
XIP_SRAM_BASE (0x1200:0000) - in this case
---- base 0x1A00:0000 = 0x1800:0000 + 0x0200:0000 (offset within 64 MB XIP address space)
bit 13 - cache way (only one way, otherwise will be re-pinned)
bits 12:3 - cache line
bits 2:0 = 0x7: Pin cache set/way at address
I can see the XIP RAM mapped at 0x1200:0000, fully populated with cache data memory.
That was my intention. Thanks !

Is there any chance to see the tag memory ?
Statistics: Posted by gmx — Thu Oct 24, 2024 1:51 pm