Eventually, provision will be made for some sort of usage of core 1 - that's why it's there.
Software engineering effort in the near term is to ensure that there are no outright regressions in feature set between Pi 0-4 (but mostly Pi 4) and Pi 5, and after that then we can start working towards supporting more niche use-cases that take more advantage of the microcontroller-like crossover features of RP1.
Careful consideration needs to be made (by us) about isolating core 1 from core 0, and proper separation of the duties imposed on each. This includes things like access to peripheral register ranges, and host memory (SDRAM).
Software engineering effort in the near term is to ensure that there are no outright regressions in feature set between Pi 0-4 (but mostly Pi 4) and Pi 5, and after that then we can start working towards supporting more niche use-cases that take more advantage of the microcontroller-like crossover features of RP1.
Careful consideration needs to be made (by us) about isolating core 1 from core 0, and proper separation of the duties imposed on each. This includes things like access to peripheral register ranges, and host memory (SDRAM).
Statistics: Posted by jdb — Wed Jan 17, 2024 7:37 pm