Thanks Fridux, every little bit helps! I know that post must have taken a long time to draft, I appreciate it.
Looks like we're doing the same thing. I did have my TCR_EL1 with TT0/TT1 as INNER SHAREABLE. Tried switching them to OUTER SHAREABLE to match yours, but no difference.
I also tried reading from my UART registers (also in device type memory) with the same problematic results. Would only/always load the first 32 bits of a 128bit memory range, no matter what offset I used. Still works fine in other areas of memory (eg, I read 0x80000 - 0x8000c, the kernel start up instructions, all four 32bit words, into S10-S13 with no problem).
I'm going to try and change memory type to standard, non-cached for the SDHOST but at that level, my MMU translation table is at 2MB blocks, so I don't have much granularity and previous efforts of switching the entire MMIO area to standard, non-cached failed to boot.
Again, I really appreciate the feedback. Will keep hacking away at it.
Looks like we're doing the same thing. I did have my TCR_EL1 with TT0/TT1 as INNER SHAREABLE. Tried switching them to OUTER SHAREABLE to match yours, but no difference.
I also tried reading from my UART registers (also in device type memory) with the same problematic results. Would only/always load the first 32 bits of a 128bit memory range, no matter what offset I used. Still works fine in other areas of memory (eg, I read 0x80000 - 0x8000c, the kernel start up instructions, all four 32bit words, into S10-S13 with no problem).
I'm going to try and change memory type to standard, non-cached for the SDHOST but at that level, my MMU translation table is at 2MB blocks, so I don't have much granularity and previous efforts of switching the entire MMIO area to standard, non-cached failed to boot.
Again, I really appreciate the feedback. Will keep hacking away at it.
Statistics: Posted by willdieh — Fri May 17, 2024 5:18 pm