Even with an "RT" kernel there will be delays. The kernel at points disable interrupts. You code/data may not be in the cache and so the cpu will have to go off to RAM to get your code. If you want a reliable solution use a Pico and PIO. If you are happy with an unreliable solution The best you can do is to have one core for the FIQ task with the code locked down in the cache. Still you will have delays as if the internal databus is being used as you write to the IO pins so there will be delayed.
Here are a few cycles out of the loop ( untested of course)
Here are a few cycles out of the loop ( untested of course)
Code:
.text.align 5 ; Align code to cache line.global sp804_handler.global sp804_handler_end; setup r13 to point to SineTablesp804_handler: eors r11, r11, #1 mov r12, #0x04000000 str r12, [r9, #0x0C] beq CountEven orr r12, r12, 0xFF str r12, [r8, #0x28] str r10, [r8, #0x1C] subs pc, lr, #4CountEven: ldrb r10, [r13],#1 str r12, [r8, #0x1C] adr R12,SineTableEnd cmp r13, r12 adreq R13,SineTable subs pc, lr, #4 SineTable:.word 0x28282726....word 0x26252424SineTableEndsp804_handler_end:Statistics: Posted by dp11 — Sat Mar 30, 2024 11:44 am