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SDK • Re: How debug a Pico without the elf?

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I don't see any 0x4001xxxx addresses? or any 32bit numbers. Those are the GPIO addresses right? maybe I have the wrong options still
There aren't any 32-bit numbers in ARM assembler, especially CortexM0 which only has 16-bit instructions and so doesn't have any instructions with immediate fields greater than 8-bit wide (apart from jumps). 32-bit constants can be loaded by a sequence of instructions, or from constant pools. With more up-scale ARMs, an arbitrary 32-bit load can be done with a pair of 32-bit instructions (With 16-bit immediates in them) which the compilers will often pick, but on CortexM0 this only makes sense for "nice" values that can be made with something like 8 bits and a shift.

So your GPIO address is probably in a constant pool. These will be harder to spot in a disassembly without symbols - the disassembler will probably have disassembled them as nonsense instructions. Constant pools are a group of 32-bit values, placed at 32-bit aligned addresses directly after a piece of code where they are used: the constant is loaded with a PC-relative load instruction.

If you know what value you are looking for, it's probably easier to find it in a hex dump than the disassembly - then go and look at the disassembly for how it's used. Note that the value loaded for the address of an I/O register may not be the exact value needing to be used: it will often load the base address of a group of I/O registers into a (CPU) register and then use an indexed load to add the small offset to the specific (I/O) register needed - this isn't directly driven by the C source, but it's a combination of the compiler's optimisation and the SDK writers building the header files to make it easy for the compiler to spot the possibility.

Here's a with-symbols disassembly of the SDK's gpio_set_function()

Code:

20002b98 <gpio_set_function>:20002b98:   4a09        ldr r2, [pc, #36]   ; (20002bc0 <gpio_set_function+0x28>)20002b9a:   0083        lsls    r3, r0, #220002b9c:   4694        mov ip, r220002b9e:   2240        movs    r2, #64 ; 0x4020002ba0:   4463        add r3, ip20002ba2:   b510        push    {r4, lr}20002ba4:   681c        ldr r4, [r3, #0]20002ba6:   00c0        lsls    r0, r0, #320002ba8:   4062        eors    r2, r420002baa:   24c0        movs    r4, #192    ; 0xc020002bac:   4014        ands    r4, r220002bae:   2280        movs    r2, #128    ; 0x8020002bb0:   0152        lsls    r2, r2, #520002bb2:   4313        orrs    r3, r220002bb4:   601c        str r4, [r3, #0]20002bb6:   4b03        ldr r3, [pc, #12]   ; (20002bc4 <gpio_set_function+0x2c>)20002bb8:   469c        mov ip, r320002bba:   4460        add r0, ip20002bbc:   6041        str r1, [r0, #4]20002bbe:   bd10        pop {r4, pc}20002bc0:   4001c004    .word   0x4001c00420002bc4:   40014000    .word   0x40014000
You can see the constant pool at 0x20002bc0 containing two constants - 4001c004, being GPIO0_CTRL and 40014000 being the base of the pad control registers, out of which it again wants the GPIO0 value at offset 4 from the base, but this time gets that with the str r1,[r0,#4] instruction - it adds the 4 as an offset rather than having it as a part of the constant. In this example, that's a completely arbitrary choice by the compiler - either way round is the same size because each constant is only used once - but it becomes more important in a larger function where the constant can be re-used.

And the corresponding source:

Code:

void gpio_set_function(uint gpio, enum gpio_function fn) {    // Set input enable on, output disable off    hw_write_masked(&padsbank0_hw->io[gpio],                   PADS_BANK0_GPIO0_IE_BITS,                   PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS    );    // Zero all fields apart from fsel; we want this IO to do what the peripheral tells it.    // This doesn't affect e.g. pullup/pulldown, as these are in pad controls.    iobank0_hw->io[gpio].ctrl = fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;

Statistics: Posted by arg001 — Tue Mar 19, 2024 9:33 am



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