Thanks, that is indeed the hint I needed to get this working. I had the chaining happen right after the active line, following the example of dvi_out_hstx_encoder, but switching it around so the order is [sync, back porch, active, front porch], I'm able to transfer 32 bits with no problem. In fact, I'm looking at 1280x720 60Hz video right now, overclocked to a cool 320MHz. I had thought that the 8-deep fifo in HSTX would absorb the chain delays, but I guess not.It is certainly possible but timing is pretty tight if you are for example chaining DMA to insert sync periods and/or data islands- I didn’t look at your code, but basically you need to make sure that these chain delays happen in the middle of a repeated HSTX symbol
I am indeed using irq/cpu to stick the signal together but I am fairly confident I can do it. I got pretty far with the 2040.
Statistics: Posted by raphlinus — Sun May 04, 2025 11:59 pm