I haven't used I2C yet on RP2040 so have no idea if this works but maybe there's a way to fake NACK. When the I2C interrupt handler runs, the I2C controller is bus stretching by bringing SCL low. It will keep doing that until it has a byte to send or receive. I wonder what would happen if, instead, in the interrupt handler, change the function of the SCL GPIO to SIO. Now the I2C master sees SCL pulled high and and proceeds to clock out the ACK bit, which if SDA is pulled high at that point, would be interpreted as NACK. Could change the function of the SDA GPIO to SIO as well to ensure it is high. This might leave the I2C controller state machine totally confused. I wonder if the multi-master stuff will think there's a bus conflict and give up.
Statistics: Posted by alastairpatrick — Thu Feb 29, 2024 2:54 am
