Would be useful, though no idea if it is possible without total redesign of the PIO in next gen device. But it would use up a location in the already rather short memory space.
A simpler alternative might be a third scratch register Z sitting in parallel to the FIFO which can only be written to by the main processor and can be loaded into X or Y as needed.
A simpler alternative might be a third scratch register Z sitting in parallel to the FIFO which can only be written to by the main processor and can be loaded into X or Y as needed.
Statistics: Posted by MikeDB — Thu Dec 19, 2024 1:38 am