on the bcm2825, there was no arm L2 cacheThat's interesting about the disabled 128K level 3 cache. I wonder if there is any situation where that would be useful.
the VPU L2 cache was put in the path of all requests, to make up for that
but starting with the bcm2836, the arm gained its own L2, and the VPU L2 was taken out of the loop, both because its smaller then the arm L2, and so the VPU doesnt have to share
but i can see how putting it back as a sort of L3, would reduce the dma latency for small buffers
flush something from the arm caches into the "L3" cache, then DMA from "L3", and you dont have to go out to dram twice
but only if the buffer fits within 128kb
and to avoid other things from swamping the 128kb "L3", you would need to map a special 16mb chunk of ram as using that L3, and other regions not
and now dma is complicated by having to work within that special region
in theory it can work, in practice, i dont know
Statistics: Posted by cleverca22 — Sun Feb 11, 2024 1:43 am