Interesting topic.
I think that CPU polling loop can be made tighter and smoother by using CBZ in assembly, especially on Cortex-M33.
I also wonder if GPIO Coprocessor could do a smarter read (masked, shifted) like Interpolator does.
Or a blocking read from GPIO, or CPU from PIO Rx FIFO.
What about generating a masked interrupt from PIO/SIO and CPU waiting in WFE, how slow is the wakeup ?
I think that CPU polling loop can be made tighter and smoother by using CBZ in assembly, especially on Cortex-M33.
I also wonder if GPIO Coprocessor could do a smarter read (masked, shifted) like Interpolator does.
Or a blocking read from GPIO, or CPU from PIO Rx FIFO.
What about generating a masked interrupt from PIO/SIO and CPU waiting in WFE, how slow is the wakeup ?
Statistics: Posted by gmx — Sun Oct 06, 2024 9:59 am
