How does the DMA event system know to proceed without the CPU? I would have expected a more traditional atomic enable flag on a multidimensional array. This would allow async behavior with synchronous control flow. Ethernet traditionally implements this on packet descriptors. DMA would need to support polling or exception to CPU to be restarted.
Four priority bits on the system interconnect and DMA was not optional. I am guessing we have QoS and not CoS. PIC32MX tried CoS briefly but PIC32MK, PIC32MZ opted out for QoS. MPU may allow some CoS but there is no IOMMU so that will have to be unprotected QoS. We would have to use monolithic kernel with user mode and trust zone.
Four priority bits on the system interconnect and DMA was not optional. I am guessing we have QoS and not CoS. PIC32MX tried CoS briefly but PIC32MK, PIC32MZ opted out for QoS. MPU may allow some CoS but there is no IOMMU so that will have to be unprotected QoS. We would have to use monolithic kernel with user mode and trust zone.
Statistics: Posted by dthacher — Wed Aug 28, 2024 4:40 pm