There should be a one-cycle improvement, because the latency between an SM pushing/popping a FIFO and the DREQ reaching the DMA was reduced by one cycle.Is there a difference (improvement) in the RP2350 PIO IN, OUT instructions <-> FIFO and DMA performance, from what it is on RP2040?
Statistics: Posted by LukeW — Sat Aug 24, 2024 4:56 pm