At boot you either have two Arm cores or two RISC-V cores, based on the architecture flag specified in your binary.
If you want a mixed configuration, you need to write the binary value 0b10 (core 1 RISC-V, core 0 Arm) or 0b01 (core 1 Arm, core 0 RISC-V) to the OTP ARCHSEL register, and then perform a watchdog reset on the cores you want to change architecture.
As for comparative performance: benchmarks are just benchmarks, I think you should try compiling your own code and checking the difference for yourself. The place where the RISC-V cores obviously lose out is anything to do with floating point, because they don't have hard FPUs and the newlib soft float (libm) support for RISC-V is not fantastic right now.
If you want a mixed configuration, you need to write the binary value 0b10 (core 1 RISC-V, core 0 Arm) or 0b01 (core 1 Arm, core 0 RISC-V) to the OTP ARCHSEL register, and then perform a watchdog reset on the cores you want to change architecture.
As for comparative performance: benchmarks are just benchmarks, I think you should try compiling your own code and checking the difference for yourself. The place where the RISC-V cores obviously lose out is anything to do with floating point, because they don't have hard FPUs and the newlib soft float (libm) support for RISC-V is not fantastic right now.
Statistics: Posted by LukeW — Thu Aug 15, 2024 2:20 pm
