You have SCL and SDA backwards.
GPIO0 is I2C0_SDA and you have it connected to pin 4 on the BMP chip, which your schematic labels as SCK.
(Also I boggle at your PCB technology choices - what looks like a 0.2mm or smaller via in a 0.4mm pad under the BMP, and vias under pairs of pads on the RP2040. Are you really paying for filled-and-plated vias with very fine annular ring tolerances, or are you just pushing this through a normal PTH process and praying that it works?).
GPIO0 is I2C0_SDA and you have it connected to pin 4 on the BMP chip, which your schematic labels as SCK.
(Also I boggle at your PCB technology choices - what looks like a 0.2mm or smaller via in a 0.4mm pad under the BMP, and vias under pairs of pads on the RP2040. Are you really paying for filled-and-plated vias with very fine annular ring tolerances, or are you just pushing this through a normal PTH process and praying that it works?).
Statistics: Posted by arg001 — Wed Jul 31, 2024 8:34 am