Has anyone attempted to measure this? The ADC chapter of the datasheet indicates that the ADC input is a sample-and-hold circuit, but does not specify how wide the sample-gate is, nor exactly when in the 96-clock sequence it occurs. You might hope that it lasts one cycle and is the first or second cycle after software has initiated a sample with CS.START_ONCE, though that's wildly speculative and it could be several cycles and/or several cycles after the start.
My interest is because I have an external mux feeding the ADC inputs, so I need to know how soon after initiating a sample I can safely switch the mux. The datasheet states that there's no settle time needed for the internal mux, and you can change AINSEL in the same register write as setting START_ONCE, so that suggests that maybe the first cycle is needed for settling.
There's also going to be some synchronization delay across the CLK_SYS/CLK_ADC boundary, so the fist cycle of the 96 isn't going to start immediately that software hits START_ONCE: that begs another question of how fast you can actually issue ADC operations in the single-shot mode - presumably not at the full 500ksamp/sec rate.
My interest is because I have an external mux feeding the ADC inputs, so I need to know how soon after initiating a sample I can safely switch the mux. The datasheet states that there's no settle time needed for the internal mux, and you can change AINSEL in the same register write as setting START_ONCE, so that suggests that maybe the first cycle is needed for settling.
There's also going to be some synchronization delay across the CLK_SYS/CLK_ADC boundary, so the fist cycle of the 96 isn't going to start immediately that software hits START_ONCE: that begs another question of how fast you can actually issue ADC operations in the single-shot mode - presumably not at the full 500ksamp/sec rate.
Statistics: Posted by arg001 — Mon Jan 29, 2024 10:43 pm