Thanks for the reply, the thing that I didn't understand is why the Rx FIFO appears to be behaving differently in both cases, as in the SDK, the flow goes Pins -> ISR -> RX FIFO -> System, by enabling the auto shift, I'd assume that as soon as the 8 bits are read, they are sent directly from the ISR to the RX FIFO, hen I could get using the pio_sm_get_blocking(), but that's not what happens.
In this code, the PIO ran 40 cycles before stalling on startup, not triggering the auto shift, then the subsequent reads would trigger the auto shift but only on 8 bits on the old data, appearing to have 1 more buffer (aka. Pins -> mysterious buffer -> ISR -> RX FIFO -> System).
In this code it worked as described in the SDK docs, after pushing 8 bits into the OSR using the put command, reading 8 bits then stalling the sm, the auto shift would move the bits from the ISR into the RX FIFO and then I could read normally.
What confuses me more is that both the ISR and the RX FIFO are 32 bits long, and my tests suggests that they were being buffered BEFORE the RX FIFO, or else I could read the data inside the FIFO without any problems, so I have no idea where those 40 bits where being buffered.
Quick note, I ditched the DMA and I'm using the get command, both the in and out auto shifts are enabled at the depth of 8 bits.
Code:
.side_set 1.wrap_target in pins, 1 side 0 nop side 1 [3].wrapCode:
.wrap_target out pins, 1 side 1 [3] in pins, 1 side 0.wrapWhat confuses me more is that both the ISR and the RX FIFO are 32 bits long, and my tests suggests that they were being buffered BEFORE the RX FIFO, or else I could read the data inside the FIFO without any problems, so I have no idea where those 40 bits where being buffered.
Quick note, I ditched the DMA and I'm using the get command, both the in and out auto shifts are enabled at the depth of 8 bits.
I'd assume you are talking about the load pin (SH/LD), and yes, I'm using another pin before triggering the clocks, I didn't think that it would be beneficial to do that inside the PIO program since that doesn't need precision nor speed, especially since I'm planning to use all 4 sm on the same PIO with different PIO programs, so I need to use as few instructions as possible, hence the need to make the 2 liner work instead of the giant code I found on the internet that does the same thingI'm also wondering how you are planning to synchronize the bits you are shifting in - I'd expect you to be using another pin to drive the nPL pin on the 74HC165, and hence needing to count the 8 bits in the PIO, where you seem happy to just shift in bits with no control over where the byte boundary lies.
Statistics: Posted by Fuguetero — Wed May 22, 2024 7:45 pm